FAST_SEL0=NC, FAST_SEL1=NC
Fast Clock Output Select Register
| FAST_SEL0 | Select signal for fast clock output #0 0 (NC): Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL0 and HFCLK_SEL0. 1 (ECO): External Crystal Oscillator (ECO) 2 (EXTCLK): External clock input (EXTCLK) 3 (ALTHF): Alternate High-Frequency (ALTHF) clock input to SRSS 4 (TIMERCLK): Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. 5 (PATH_SEL0): Selects the clock path chosen by PATH_SEL0 field 6 (HFCLK_SEL0): Selects the output of the HFCLK_SEL0 mux 7 (SLOW_SEL0): Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL0 |
| PATH_SEL0 | Selects a clock path to use in fast clock output #0 logic. For FLL path, it connects after the bypass mux. For PLL path(s), it connects after the CLK_PLL_DDFT mux. 0: FLL output 1-15: PLL output on path1-path15 (if available) |
| HFCLK_SEL0 | Selects a HFCLK tree for use in fast clock output #0 |
| FAST_SEL1 | Select signal for fast clock output #1 0 (NC): Disabled - output is 0. For power savings, clocks are blocked before entering any muxes, including PATH_SEL1 and HFCLK_SEL1. 1 (ECO): External Crystal Oscillator (ECO) 2 (EXTCLK): External clock input (EXTCLK) 3 (ALTHF): Alternate High-Frequency (ALTHF) clock input to SRSS 4 (TIMERCLK): Timer clock. It is grouped with the fast clocks because it may be a gated version of a fast clock, and therefore may have a short high pulse. 5 (PATH_SEL1): Selects the clock path chosen by PATH_SEL1 field 6 (HFCLK_SEL1): Selects the output of the HFCLK_SEL1 mux 7 (SLOW_SEL1): Selects the output of CLK_OUTPUT_SLOW.SLOW_SEL1 |
| PATH_SEL1 | Selects a clock path to use in fast clock output #1 logic. For FLL path, it connects after the bypass mux. For PLL path(s), it connects after the CLK_PLL_DDFT mux. 1-15: PLL output on path1-path15 (if available) |
| HFCLK_SEL1 | Selects a HFCLK tree for use in fast clock output #1 logic |